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Honeywell's FPGA to ASIC Conversion and Replacement Services |  |
As part of Honeywell's commitment to help technology development teams meet program reliability and mission requirements, Honeywell has developed a cost-effective validated path to convert or replace Field Programmable Gate Arrays (FPGAs) with our highly reliable Application Specific Integrated Circuits (ASICs). |
| Why invest in converting FPGAs to ASICs? |
 | | Reduced single event upsets and total dose risks, |  | | Increased performance speeds and capacity, |  | | Lower power dissipation, |  | | Reduced number of components on a system |
FPGA to ASIC Conversion and Replacement Deliverables Honeywell has developed an accelerated FPGA replacement model to convert FPGA designs into Honeywell's high-reliability gate array-based application specific integrated circuits (ASICs). Many designs have used Honeywell's FPGA replacement flow and demonstrated on-time delivery of PODs and flight units. A summary of the services Honeywell provides include: |
 | | Conversion from FPGA design code to Honeywell's Silicon On Insulator-based netlist design |  | | Quick-turn development model designed to reduce cycle time |  | | Optional services also available to quickly translate FPGA netlist to Honeywell netlist |  | | QML-qualified packaging for pin-for-pin FPGA compatibility |  | | Testing and screening |
Design Translation Honeywell will convert FPGAs from several design stages to Honeywell netlist. To take advantage of Honeywell's accelerated development cycle, the following considerations and deliverables are recommended to streamline flow: |
 | | Existing FPGA must be fully functional. |  | | Honeywell provides timing closure on design in place and route. |  | | Honeywell provides streamlined, scaled AC/DC testing. |  | | Customer provides the following: |
| |  | | Test vectors at PDR | | |  | | Prime Time constraint file at PDR | | |  | | Two programmable FPGA parts |
Overall design services include:  | | Preliminary design review & critical test review |  | | PDR/CTR held concurrently to reduce test cycle time |  | | Close post route timing (performed by Honeywell) |  | | Critical Design Review |  | | Provide timing results and design database for customer review |  | | Release to mask |
Leadership Technologies and Best-In-Class Manufacturing Honeywell's proven SOI radiation resistant technology is the preferred path for many system designers considering a FPGA replacement. Our HX2000 and HX3000 technologies are implemented in many space and aerospace applications. These technologies are well suited for the FPGA conversion due to performance, gate count and reliability. Honeywell offers two gate array options from our portfolio for aerospace FPGA-conversion applications. Our HX5000 150nm standard cell product family provides a high performance, high gate count ASIC flight solution conversion for systems prototyped with FPGAs. |
 | | Performance oriented sea-of-transistor array, fabricated on Honeywell's 0.7µ Silicon On Insulator (SOI) process. |  | | Developed with 3-metal layer fabrication process. |  | | 1E-10 SEU and 1Mrad total dose tolerant. |  | | Supports 2.5V or 3.3V core operation (true 3.3V, true 5V and 5V tol.). |  | | Supports system speeds beyond 100 MHz. |  | | Four package options to satisfy drop-in board replacement. |
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| HX3000 Gate Array (HX306g) |
 | | Very high-density gate arrays, fabricated on Honeywell's 0.35µ Silicon On Insulator (SOI) process. |  | | Developed with 4-metal layer fabrication process. |  | | 440k usable gates. |  | | 1E-11 SEU and 1Mrad/300 Krad total dose tolerant. |  | | Supports 2.5V or 3.3V core operation. |  | | Supports system speeds beyond 250 MHz. |  | | Four package options to satisfy drop-in board replacement. |
| HX5000 Standard Cell ASICs |
 | | 150nm SOI process |  | | Gate counts up to 15M |  | | 6 or 8-metal layers |  | | 1E-11 SEU and 1Mrad Krad total dose |  | | 1.8V core, 2.5 0r 3.3 IO |  | | Supports core system speeds beyond 500 MHz |
Pin-For-Pin Replacement Packages Honeywell has access to hundreds of QML-certified packaging models to meet board specifications and reduce risk. To quickly meet development schedules, four package styles have been designed for pin-for-pin and dimensional equivalence of standard FPGA packages. These packages are Ceramic Quad Flat Packs (CQFP) and come in several configurations. |
 | | 208 Lead CQFP - 175 Signal I/O |  | | 208 Lead CQFP - 172 Signal I/O |  | | 256 Lead CQFP - 214 Signal I/O |  | | 256 Lead CQFP - 229 Signal I/O | Other features: | | Package height 3.9 mm max., including capacitors |  | | Added sites for 10-16 0.1µF decoupling capacitors |  | | Designed as cavity-up, without heat sink, 0.5mm lead pitch |  | | Thermal resistance, junction-to-case (bottom of package) |
| |  | | 0.8 °C/W with eutectic die attach | | |  | | 1.6 °C/W with JM7800 adhesive die attach |
 | | QML-certified package design rules, material specifications, and assembly process |
Testing and Screening Honeywell has developed a streamlined test flow to reduce turnaround time and greatly reduce cycle time risk due to debug concerns. Our streamlined AC/DC testing model at the wafer level is designed to shorten cycle time and eliminate need for AC or DC tests of application logic: |
 | | Standard AC/DC acceptance structures to validate performance at wafer probe. |  | | Test early chip across temperature to correlate wafer probe to mil-temp. |  | | Pin-by-pin tri-state leakage measurements @ wafer probe and package testing. |  | | Supports QML V & Q |
The accelerated model includes the following functional package test sequences:  | | Minimal or no functional tests of application logic |  | | ATPG tests of application |  | | IDDQ test (based on scan vectors) |  | | Limited parametric tests |
Qualification and Reliability Honeywell has established a reputation for excellence by continually meeting the customer's most demanding specifications. Our mission is to exceed customer expectations in quality and to maintain the highest integrity of products and services. Even our accelerated FPGA replacement model incorporates Controlled Processes including design configuration control board, assembly configuration control board and in-line silicon process testing with SPC and continuous improvements. Periodic Testing can include Group B, D and E tests and life testing on ASICs and our standard products such as SRAMs. All processes are documented and controlled to ensure devices meet all requirements and demonstrate 100 FITs for production upgrade. Honeywell ensures that the Technology Review Board (TRB) reviews major changes and upgrades.
To immediately benefit from Honeywell's quick-turn FPGA replacement services, contact a Honeywell Applications Engineer today. |
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