#ifndef CYGONCE_PKGCONF_HAL_ARM_AT91SAM7_H
#define CYGONCE_PKGCONF_HAL_ARM_AT91SAM7_H
/*
 * File <pkgconf/hal_arm_at91sam7.h>
 *
 * This file is generated automatically by the configuration
 * system. It should not be edited. Any changes to this file
 * may be overwritten.
 */

#define CYGHWR_HAL_ARM_AT91SAM7 at91sam7se32
#define CYGHWR_HAL_ARM_AT91SAM7_at91sam7se32
#define CYGHWR_HAL_ARM_AT91SAM7SE 1
#define CYGNUM_HAL_RTC_CONSTANTS 1
#define CYGNUM_HAL_RTC_NUMERATOR 1000000000
#define CYGNUM_HAL_RTC_NUMERATOR_1000000000
#define CYGNUM_HAL_RTC_DENOMINATOR 400
#define CYGNUM_HAL_RTC_DENOMINATOR_400
#define CYGNUM_HAL_RTC_PERIOD 3750
#define CYGNUM_HAL_RTC_PERIOD_3750
#define CYGNUM_HAL_ARM_AT91_IMAGE_ADDRESS 0x00100000
#define CYGNUM_HAL_ARM_AT91_IMAGE_ADDRESS_0x00100000
#define CYGHWR_HAL_ARM_AT91SAM7_EXTRAM_LENGTH 0x00200000
#define CYGHWR_HAL_ARM_AT91SAM7_EXTRAM_LENGTH_0x00200000
#define CYGHWR_HAL_ARM_AT91SAM7_EXTROM_LENGTH 0x00100000
#define CYGHWR_HAL_ARM_AT91SAM7_EXTROM_LENGTH_0x00100000
#define CYGNUM_HAL_ARM_AT91_CLOCK_XIN_FREQ_MAX 20000000
#define CYGNUM_HAL_ARM_AT91_CLOCK_XIN_FREQ_MAX_20000000
#define CYGNUM_HAL_ARM_AT91_CLOCK_OSC_MAIN 16000000
#define CYGNUM_HAL_ARM_AT91_CLOCK_OSC_MAIN_16000000
#define CYGNUM_HAL_ARM_AT91_CLOCK_TYPE CRYSTAL
#define CYGNUM_HAL_ARM_AT91_CLOCK_TYPE_CRYSTAL
#define CYGNUM_HAL_ARM_AT91_PMC_MOR_OSCCOUNT 64
#define CYGNUM_HAL_ARM_AT91_PMC_MOR_OSCCOUNT_64
#define CYGNUM_HAL_ARM_AT91_CLOCK_SPEED 48000000
#define CYGNUM_HAL_ARM_AT91_CLOCK_SPEED_48000000
#define CYGNUM_HAL_ARM_AT91_PLL_DIVIDER 1
#define CYGNUM_HAL_ARM_AT91_PLL_DIVIDER_1
#define CYGNUM_HAL_ARM_AT91_PLL_MULTIPLIER 6
#define CYGNUM_HAL_ARM_AT91_PLL_MULTIPLIER_6
#define CYGNUM_HAL_ARM_AT91_PLL_COUNT 16
#define CYGNUM_HAL_ARM_AT91_PLL_COUNT_16
#define CYGNUM_HAL_ARM_AT91_SLOW_CLOCK 32768
#define CYGNUM_HAL_ARM_AT91_SLOW_CLOCK_32768
#define CYGNUM_HAL_ARM_AT91SAM7A_CLOCK_SPEED 80000000
#define CYGNUM_HAL_ARM_AT91SAM7A_CLOCK_SPEED_80000000
#define CYGNUM_HAL_ARM_AT91SAM7A_PLL_MULTIPLIER 10
#define CYGNUM_HAL_ARM_AT91SAM7A_PLL_MULTIPLIER_10
#define CYGNUM_HAL_ARM_AT91SAM7A_PLL_DIVIDER 2
#define CYGNUM_HAL_ARM_AT91SAM7A_PLL_DIVIDER_2
#define CYGNUM_HAL_ARM_AT91SAM7A_LFCLK_DIVIDER 64
#define CYGNUM_HAL_ARM_AT91SAM7A_LFCLK_DIVIDER_64
#define CYGNUM_HAL_ARM_AT91SAM7A_LFCLOCK_SPEED 250000
#define CYGNUM_HAL_ARM_AT91SAM7A_LFCLOCK_SPEED_250000
#define CYGNUM_HAL_ARM_AT91SAM7A_RTCLK 32768
#define CYGNUM_HAL_ARM_AT91SAM7A_RTCLK_32768
#define CYGBLD_GLOBAL_OPTIONS 1

#endif
