#ifndef CYGONCE_DEVS_CSB337_ETH_INL
#define CYGONCE_DEVS_CSB337_ETH_INL
//==========================================================================
//
//      csb337_eth.inl
//
//      Hardware specifics for Cogent CSB337 ethernet support
//
//==========================================================================
// ####ECOSGPLCOPYRIGHTBEGIN####                                            
// -------------------------------------------                              
// This file is part of eCos, the Embedded Configurable Operating System.   
// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
// Copyright (C) 2003 eCosCentric Limited                                   
//
// eCos is free software; you can redistribute it and/or modify it under    
// the terms of the GNU General Public License as published by the Free     
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// version.                                                                 
//
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
// for more details.                                                        
//
// You should have received a copy of the GNU General Public License        
// along with eCos; if not, write to the Free Software Foundation, Inc.,    
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
//
// As a special exception, if other files instantiate templates or use      
// macros or inline functions from this file, or you compile this file      
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// this file does not by itself cause the resulting work to be covered by   
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// General Public License v2.                                               
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// ####ECOSGPLCOPYRIGHTEND####                                              
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    eCosCentric
// Contributors: eCosCentric
// Date:         2003-08-19
// Purpose:      
// Description:  
//              
//####DESCRIPTIONEND####
//
//==========================================================================

#include CYGDAT_DEVS_AT91RM9200_ETH_CDL

#ifdef CYGHWR_DEVS_ETH_ARM_CSB337_ETH0
ETH_PHY_REG_LEVEL_ACCESS_FUNS(eth0_phy, 
                              at91rm9200_eth_phy_init,
                              NULL,
                              at91rm9200_eth_phy_put_reg,
                              at91rm9200_eth_phy_get_reg);

// Align buffers on a cache boundary
#define RxBUFSIZE CYGNUM_DEVS_ETH_ARM_AT91RM9200_RxNUM*CYGNUM_DEVS_ETH_ARM_AT91RM9200_BUFSIZE
#define TxBUFSIZE CYGNUM_DEVS_ETH_ARM_AT91RM9200_TxNUM*CYGNUM_DEVS_ETH_ARM_AT91RM9200_BUFSIZE
#if 0
// These buffers are not actually used. Instead they are allocated explicitly in the on-chip
// SRAM at 0x70000000. This is because the buffers themselves work best in SRAM, and the RX
// buffer descriptor table must be aligned on a 64byte boundary. The SRAM is 16k, which is
// enough for 2 Tx buffers, 8 Rx Buffers plus the RX descriptor table, but not much else.
static unsigned char at91rm9200_eth_rxbufs[RxBUFSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
static unsigned char at91rm9200_eth_txbufs[TxBUFSIZE] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
static bd_t at91rm9200_eth_rxbd[CYGNUM_DEVS_ETH_ARM_AT91RM9200_RxNUM] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));
#endif
static bd_t at91rm9200_eth_txbd[CYGNUM_DEVS_ETH_ARM_AT91RM9200_TxNUM] __attribute__((aligned(HAL_DCACHE_LINE_SIZE)));

static struct at91rm9200_eth_info at91rm9200_eth0_info = {
    0, // Interrupt vector
    "eth0_esa",
    { 0x00, 0x23, 0x31, 0x37, 0x00, 0x1C}, // Default ESA
    CYGNUM_DEVS_ETH_ARM_AT91RM9200_RxNUM,  // Number of Rx buffers
    (unsigned char *)0x70000D00,           // Rx buffer space in SRAM
    (bd_t *)0x70000000,                    // Rx buffer headers in SRAM
    CYGNUM_DEVS_ETH_ARM_AT91RM9200_TxNUM,  // Number of Tx buffers
    (unsigned char *)0x70000100,           // Tx buffer space in SRAM
    at91rm9200_eth_txbd,                   // Tx buffer headers
    &eth0_phy,                             // PHY access routines
};

ETH_DRV_SC(at91rm9200_eth0_sc,
           &at91rm9200_eth0_info,  // Driver specific data
           "eth0",                 // Name for this interface
           at91rm9200_eth_start,
           at91rm9200_eth_stop,
           at91rm9200_eth_control,
           at91rm9200_eth_can_send,
           at91rm9200_eth_send,
           at91rm9200_eth_recv,
           at91rm9200_eth_deliver,
           at91rm9200_eth_int,
           at91rm9200_eth_int_vector);

NETDEVTAB_ENTRY(at91rm9200_netdev, 
                "at91rm9200_eth", 
                at91rm9200_eth_init, 
                &at91rm9200_eth0_sc);

#ifdef CYGPKG_REDBOOT
#include <pkgconf/redboot.h>
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
#include <redboot.h>
#include <flash_config.h>
RedBoot_config_option("Network hardware address [MAC]",
                      eth0_esa,
                      ALWAYS_ENABLED, true,
                      CONFIG_ESA, &at91rm9200_eth0_info.enaddr
    );
#endif // CYGSEM_REDBOOT_FLASH_CONFIG
#endif // CYGPKG_REDBOOT

#endif // CYGHWR_DEVS_ETH_ARM_CSB337_ETH0

#endif  // CYGONCE_DEVS_CSB337_ETH_INL
// ------------------------------------------------------------------------
