//==========================================================================
//
//      lm3s8962_eval_spi.c
//
//      Support for the SPI devices on LM3S8962-EVAL board
//
//==========================================================================
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// -------------------------------------------                              
// This file is part of eCos, the Embedded Configurable Operating System.   
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// Copyright (C) 2008 eCosCentric Limited                                   
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//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   nickg
// Date:        2008-02-27
//
//####DESCRIPTIONEND####
//=============================================================================

#include <pkgconf/hal.h>
#include <pkgconf/io_spi.h>
#include <pkgconf/hal_cortexm_lm3s_lm3s8962_eval.h>

#include <cyg/hal/hal_io.h>
#include <cyg/hal/hal_intr.h>

#include <cyg/infra/cyg_type.h>
#include <cyg/io/spi.h>
#include <cyg/io/spi_pl022.h>

// -------------------------------------------------------------------------
// SPI bus 0

static cyg_uint32 cyg_spi_lm3s_bus0_cs_pins[] = { CYGDAT_HAL_CORTEXM_LM3S_SPI0_CS_PINS };

cyg_spi_pl022_bus_t cyg_spi_lm3s_bus0 =
{
    .spi_bus.spi_transaction_begin    = cyg_spi_pl022_transaction_begin,
    .spi_bus.spi_transaction_transfer = cyg_spi_pl022_transaction_transfer,
    .spi_bus.spi_transaction_tick     = cyg_spi_pl022_transaction_tick,
    .spi_bus.spi_transaction_end      = cyg_spi_pl022_transaction_end,
    .spi_bus.spi_get_config           = cyg_spi_pl022_get_config,
    .spi_bus.spi_set_config           = cyg_spi_pl022_set_config,
    
    .interrupt_number                 = CYGNUM_HAL_INTERRUPT_SSI0,
    .interrupt_priority               = 0x50,
    .base                             = CYGHWR_HAL_LM3S_SSI0,
    .bus_num                          = 0,
    .enable                           = CYGHWR_HAL_LM3S_SPI0_CLOCK,
    .sclk_pin                         = CYGHWR_HAL_LM3S_SPI0_SCLK,
    .miso_pin                         = CYGHWR_HAL_LM3S_SPI0_MISO,
    .mosi_pin                         = CYGHWR_HAL_LM3S_SPI0_MOSI,
    .cs_pin                           = &cyg_spi_lm3s_bus0_cs_pins[0],
    .cs_count                         = sizeof(cyg_spi_lm3s_bus0_cs_pins)/sizeof(cyg_uint32),
};

CYG_SPI_DEFINE_BUS_TABLE( cyg_spi_pl022_device_t, 0 );

// -------------------------------------------------------------------------
// Aardvark SPI test board, with AT2050A connected on Bus 0, chip select 0

#ifdef CYGPKG_IO_TESTING_AARDVARK
# include <pkgconf/io_testing_aardvark.h>
# ifdef CYGHWR_IO_TESTING_AARDVARK_SPI

cyg_spi_pl022_device_t cyg_aardvark_at25080 CYG_SPI_DEVICE_ON_BUS(0) = 
{
    .spi_device.spi_bus = &cyg_spi_lm3s_bus0.spi_bus,

    .dev_num     = 0,       // Device number
    .cl_pol      = 0,       // Clock polarity (0 or 1)
    .cl_pha      = 0,       // Clock phase (0 or 1)
    .cl_brate    = 10000000, // Clock baud rate. At 3.3v 10MHz is allowed for this part.
//    .cl_brate    = 1000000, // Clock baud rate. At 3.3v 10MHz is allowed for this part.
    .cs_up_udly  = 1,       // Delay in usec between CS up and transfer start.
                            // Tcss (CS setup time) for this part at 3.3V is 250ns.
    .cs_dw_udly  = 1,       // Delay in usec between transfer end and CS down
                            // Tcsh (CS hold time) for this part at 3.3V is 250ns.
    .tr_bt_udly  = 1        // Delay in usec between two transfers
                            // Tcs (CS high time) for this part at 3.3V is 250ns.
};
# endif
#endif

//=============================================================================
// EOF lm3s8962_eval_spi.c
