eCosPro® Reference Manual
Prev |  | Next

# The HAL Port

## Name

HAL Port -- Implementation Details

## Overview

This documentation explains how the eCos HAL specification has been mapped onto the AT91RM9200-EK/DK hardware, and should be read in conjunction with that specification. The AT91RM9200-EK/DK platform HAL package complements the ARM architectural HAL, the ARM9 variant HAL and the AT91RM9200 processor HAL. It provides functionality which is specific to the target board.

## Startup

Following a hard or soft reset, the HAL will initialize or reinitialize most of the on-chip peripherals. There is an exception for RAM startup applications which depend on a ROM monitor for certain services.

For ROM or ROMRAM startup, the HAL will perform additional initialization, setting up the external RAM and programming the various internal registers. This is all done in the `PLATFORM_SETUP1` macro in the assembler header file `hal_platform_setup.h`.

## Linker Scripts and Memory Maps

The platform HAL package provides the memory layout information needed to generate the linker script. The key memory locations are as follows:

Flash

  This is located at address 0x10000000 of the physical memory space. The HAL uses the MMU to locate it at virtual address 0x60000000 after initialization. It remains accessible at address 0x1000000 but accesses to this address range are uncached.

SDRAM

  This is located at address 0x20000000 of the physical memory space. The HAL configures the MMU to retain the SDRAM at virtual address 0x20000000, but in order to assign hardware exception vectors vectors at address 0x00000000, the HAL also uses the MMU to create a clone of this memory at virtual address 0x00000000. The same memory is also accessible uncached and unbuffered at virtual location 0x30000000 for use by devices. The first 32 bytes are used for hardware exception vectors. The next 32 bytes are used for the VSR table and the next 256 bytes are normally used for the eCos virtual vectors, allowing RAM-based applications to use services provided by the ROM monitor. Memory is required for the MMU tables, and must be aligned on a 16Kbyte boundary. These therefore occupy memory from 0x4000 to 0x8000. For ROM/ROMRAM startup, all remaining SDRAM is available. For RAM startup, available RAM starts at virtual location 0x00040000, with the bottom 256kB reserved for use by RedBoot.

On-chip SRAM

  This is located at address 0x00200000 of the physical memory space. However the HAL uses the MMU to relocate this to virtual address 0x70000000. The same memory is also accessible uncached and unbuffered at virtual location 0x70100000 for use by devices. At present this memory is entirely reserved for use by the ethernet interface, since there are problems using external SDRAM for ethernet buffers.

On-chip ROM

  This is located at address 0x00100000 of the physical memory space. However the HAL uses the MMU to relocate this to virtual address 0x71000000. The same memory is also accessible uncached and unbuffered at virtual location 0x71800000.

USB host port

  The USB host port (UHP) registers are located at address 0x00300000 of the physical memory space. However the HAL uses the MMU to relocate this to virtual address 0x72800000. Memory accessed at this address is uncached and unbuffered. There is no cached variant.

SPI dataflash

  SPI Dataflash media can only be accessed with the Flash API. For the purposes of this API a placeholder address range has been allocated as if the Flash is present at this address. The base of this address range is 0x30000000 and the extent will clearly depend on the Dataflash capacity. This reserved range is not real memory and any attempt to access it directly by the processor other than via the Flash API will result in a memory address exception.

On-chip Peripheral Registers

  These are located at address 0xFF000000 in the physical memory space. When the MMU is enabled, it sets up a direct, uncached, unbuffered mapping so that these registers remain accessible at their physical locations.

Off-chip Peripherals

  eCos uses the SDRAM, parallel NOR flash, ethernet PHY, SPI dataflash and MCI facilities on the AT91RM9200-EK/DK boards. eCos does not currently make any use of any other off-chip peripherals present on these boards.

## Advanced Interrupt Controller

This port has been designed to exploit benefits of the Advanced Interrupt Controller of the AT91RM9200, using the facilities of the AT91RM9200 processor HAL. Consult the documentation in that package for details.

## SPI Dataflash

eCos supports SPI access to Dataflash on the AT91RM9200. Two physical slots are provided on the board, but only the upper one may be used for SPI dataflash, not the one on the underside. This is due to an AT91RM9200 errata affecting SPI chip selects.

Accesses to Dataflash are performed via the Flash API, using 0x30000000 as the nominal address of the device, although it does not truly exist in the processor address space. On driver initialisation, eCos and RedBoot can detect the presence of a card in the socket. In particular, on reset RedBoot will indicate the presence of Flash at the 0x30000000 address range in its startup banner if it has been successfully detected. Hot swapping is not possible.

Since Dataflash is not directly addressable, access from RedBoot is only possible using fis command operations. Flash partitions within the FIS can be created, although users should be aware that the FIS partition data is stored in the NOR flash, and not on a per-Dataflash card basis. Therefore if a second Dataflash card is inserted it will appear to have the same FIS partitions residing on the card. Care must be taken if swapping between cards with differing partition layouts.

The MCI driver cannot be enabled simultaneously with the SPI driver, as the drivers need differing pin configurations for the same pins on this board due to the shared socket.

## Real-time characterization

The tm_basic kernel test gives statistics gathered about the real-time characterization and performance of the kernel. The sample output is shown here for information. The test was built in ARM mode, which provided better performance than Thumb mode.

                Startup, main stack : stack used   412 size  3920
                 Startup :  Interrupt stack used   524 size  4096
                 Startup : Idlethread stack used    80 size  2048

    eCos Kernel Timings
    Notes: all times are in microseconds (.000001) unless otherwise stated

    Reading the hardware clock takes 0 'ticks' overhead
    ... this value will be factored out of all other measurements
    Clock interrupt took   13.02 microseconds (6 raw clock ticks)

    Testing parameters:
       Clock samples:            32
       Threads:                  64
       Thread switches:         128
       Mutexes:                  32
       Mailboxes:                32
       Semaphores:               32
       Scheduler operations:    128
       Counters:                 32
       Flags:                    32
       Alarms:                   32

                                     Confidence
         Ave     Min     Max     Var  Ave  Min  Function
      ======  ======  ======  ====== ========== ========
       14.09    8.55   19.23    2.46   45%  25% Create thread
        2.10    0.00    4.27    0.13   95%   3% Yield thread [all suspended]
        2.74    2.14    6.41    0.88   73%  73% Suspend [suspended] thread
        2.54    2.14    4.27    0.65   81%  81% Resume thread
        3.30    2.14    6.41    1.09   51%  46% Set priority
        0.47    0.00    2.14    0.73   78%  78% Get priority
        7.24    6.41   14.96    1.09   65%  65% Kill [suspended] thread
        2.10    0.00    4.27    0.13   95%   3% Yield [no other] thread
        4.21    2.14    6.41    0.19   93%   4% Resume [suspended low prio] thread
        2.40    2.14    4.27    0.47   87%  87% Resume [runnable low prio] thread
        2.94    2.14    4.27    1.00   62%  62% Suspend [runnable] thread
        2.14    0.00    4.27    0.07   96%   1% Yield [only low prio] thread
        2.17    2.14    4.27    0.06   98%  98% Suspend [runnable->not runnable]
        7.08    6.41   12.82    0.96   71%  71% Kill [runnable] thread
        5.41    4.27    8.55    1.10   50%  48% Destroy [dead] thread
       10.32    8.55   14.96    0.72   78%  20% Destroy [runnable] thread
       12.69   10.68   19.23    0.81   70%  20% Resume [high priority] thread
        5.56    4.27    8.55    1.04   58%  40% Thread switch

        0.52    0.00    2.14    0.78   75%  75% Scheduler lock
        1.77    0.00    2.14    0.61   82%  17% Scheduler unlock [0 threads]
        1.77    0.00    2.14    0.61   82%  17% Scheduler unlock [1 suspended]
        1.77    0.00    2.14    0.61   82%  17% Scheduler unlock [many suspended]
        1.78    0.00    4.27    0.61   82%  17% Scheduler unlock [many low prio]

        0.87    0.00    2.14    1.03   59%  59% Init mutex
        2.74    2.14    6.41    0.90   75%  75% Lock [unlocked] mutex
        3.07    2.14    4.27    1.05   56%  56% Unlock [locked] mutex
        2.34    2.14    4.27    0.36   90%  90% Trylock [unlocked] mutex
        2.14    2.14    2.14    0.00  100% 100% Trylock [locked] mutex
        0.53    0.00    2.14    0.80   75%  75% Destroy mutex
       12.89   12.82   14.96    0.13   96%  96% Unlock/Lock mutex

        0.80    0.00    4.27    1.05   65%  65% Create mbox
        0.80    0.00    2.14    1.00   62%  62% Peek [empty] mbox
        2.60    2.14    4.27    0.73   78%  78% Put [first] mbox
        0.33    0.00    2.14    0.56   84%  84% Peek [1 msg] mbox
        2.67    2.14    4.27    0.80   75%  75% Put [second] mbox
        0.53    0.00    2.14    0.80   75%  75% Peek [2 msgs] mbox
        2.60    2.14    4.27    0.73   78%  78% Get [first] mbox
        2.47    2.14    4.27    0.56   84%  84% Get [second] mbox
        2.47    2.14    4.27    0.56   84%  84% Tryput [first] mbox
        2.20    2.14    4.27    0.13   96%  96% Peek item [non-empty] mbox
        2.54    2.14    4.27    0.65   81%  81% Tryget [non-empty] mbox
        2.07    0.00    2.14    0.13   96%   3% Peek item [empty] mbox
        2.20    2.14    4.27    0.13   96%  96% Tryget [empty] mbox
        0.47    0.00    2.14    0.73   78%  78% Waiting to get mbox
        0.47    0.00    2.14    0.73   78%  78% Waiting to put mbox
        2.67    2.14    6.41    0.83   78%  78% Delete mbox
        6.61    6.41   12.82    0.38   96%  96% Put/Get mbox

        0.73    0.00    2.14    0.96   65%  65% Init semaphore
        2.20    0.00    4.27    0.26   90%   3% Post [0] semaphore
        2.20    2.14    4.27    0.13   96%  96% Wait [1] semaphore
        2.00    0.00    2.14    0.25   93%   6% Trywait [0] semaphore
        2.07    0.00    2.14    0.13   96%   3% Trywait [1] semaphore
        0.73    0.00    2.14    0.96   65%  65% Peek semaphore
        0.33    0.00    2.14    0.56   84%  84% Destroy semaphore
        7.28    6.41   10.68    1.08   62%  62% Post/Wait semaphore

        1.00    0.00    2.14    1.06   53%  53% Create counter
        0.93    0.00    2.14    1.05   56%  56% Get counter value
        0.60    0.00    2.14    0.86   71%  71% Set counter value
        2.74    2.14    4.27    0.86   71%  71% Tick counter
        0.53    0.00    2.14    0.80   75%  75% Delete counter

        0.73    0.00    2.14    0.96   65%  65% Init flag
        2.54    2.14    4.27    0.65   81%  81% Destroy flag
        2.00    0.00    4.27    0.38   87%   9% Mask bits in flag
        2.40    2.14    4.27    0.47   87%  87% Set bits in flag [no waiters]
        3.40    2.14    6.41    1.11   53%  43% Wait for flag [AND]
        3.27    2.14    4.27    1.06   53%  46% Wait for flag [OR]
        3.27    2.14    4.27    1.06   53%  46% Wait for flag [AND/CLR]
        3.34    2.14    4.27    1.05   56%  43% Wait for flag [OR/CLR]
        0.40    0.00    2.14    0.65   81%  81% Peek on flag

        1.53    0.00    2.14    0.86   71%  28% Create alarm
        4.41    2.14    8.55    0.51   84%   6% Initialize alarm
        2.00    0.00    4.27    0.38   87%   9% Disable alarm
        4.34    4.27    6.41    0.13   96%  96% Enable alarm
        2.40    2.14    4.27    0.47   87%  87% Delete alarm
        3.14    2.14    4.27    1.06   53%  53% Tick counter [1 alarm]
       14.69   12.82   14.96    0.47   87%  12% Tick counter [many alarms]
        5.01    4.27    6.41    0.96   65%  65% Tick & fire counter [1 alarm]
       86.34   85.47   87.61    1.03   59%  59% Tick & fire counters [>1 together]
       16.89   14.96   17.09    0.36   90%   9% Tick & fire counters [>1 separately]
       10.75   10.68   19.23    0.13   99%  99% Alarm latency [0 threads]
       13.59   10.68   21.37    1.64   76%  22% Alarm latency [2 threads]
       13.89   10.68   25.64    1.30   92%   4% Alarm latency [many threads]
       19.63   19.23   61.97    0.77   96%  96% Alarm -> thread resume latency

        2.15    2.14    6.41    0.00            Clock/interrupt latency

        5.05    2.14    8.55    0.00            Clock DSR latency

       48       0     296  (main stack:  1408)  Thread stack used (1360 total)
               All done, main stack : stack used  1408 size  3920
                All done :  Interrupt stack used   208 size  4096
                All done : Idlethread stack used   732 size  2048

    Timing complete - 29590 ms total

    PASS:<Basic timing OK>
    EXIT:<done>

## Other Issues

The AT91RM9200-EK/DK platform HAL does not affect the implementation of other parts of the eCos HAL specification. The AT91RM9200 processor HAL, ARM9 variant HAL, and the ARM architectural HAL documentation should be consulted for further details.

Prev | Home | Next
JTAG debugging support | Up | Cogent CSB337 Board Support